1. Field of the Invention
The present invention relates to a signal processing circuit, and in particular to a signal processing circuit capable of performing two or more types of circuit operations.
2. Description of the Related Art
Data processing conventionally required by many of communication standards such W-CDMA as a mobile communication standard, and IEEE802.11a or IEEE802.11b as a wireless LAN standard has been carried out by using scrambler, convolutional encoder, cyclic redundancy check (CRC) circuit, quasi-random encoder based on linear feedback shift register and so forth. There are also adopted a Viterbi decoder, a matched filter, and fast Fourier transformation (FFT) composed of a butterfly routine executing complex multiplication and complex summation.
Patent Documents 1 and 2 listed below respectively describe a quasi random number generating circuit using a linear feedback shift register. Patent Document 3 listed below describes a variable CRC generation circuit. Patent Document 4 listed below describes a scrambler.    [Patent Document 1] Japanese Patent Application Laid-Open No. Sho 63-67628    [Patent Document 2] Japanese Patent Application Laid-Open No. Sho 63-204919    [Patent Document 3] Japanese Patent Application Laid-Open No. Hei 4-292018    [Patent Document 4] Japanese Patent Application Laid-Open No. Hei 3-52432
The conventional scrambler and CRC generator are configured as separate fixed circuits because of their differences in the processing. It has also been necessary for the conventional scrambler and CRC generator to modify position or the number of taps depending on every different communication standard. As a consequence, the scramblers, for example, even having the same function should have been configured by hardware dedicated for the individual communication standards, and by the separate fixed circuits.